Todd Havekost - 20 June 2016

With the recent release of “Alice Through the Looking Glass” (my wife is a huge Johnny Depp fan), it seems only appropriate to write on a subject epitomized by Alice’s famous words:

“What if I should fall right through the center of the earth … oh, and come out the other side, where people walk upside down?”  (Lewis Carroll, Alice in Wonderland)

Mainframe Peak Utilization

Along with the vast majority of the mainframe community, I had long embraced the perspective that running mainframes at high levels of utilization was essential to operating in the most cost-effective manner.

Based on carefully constructed capacity forecasts, our established process involved implementing just-in-time upgrades designed to ensure peak utilization’s remained slightly below 90%.

MSU Consumption Spikes

It turns out we’ve all been wrong. After implementing z13 processor upgrades and observing MSU consumption spike up sharply, I learned first-hand the dramatic impact processor cache utilization has on delivered capacity for z13 models.

When processor cache is optimized, our high-powered mainframe processors remain productive actively executing instructions, rather than unproductively burning cycles waiting for data and instructions to be staged into the Level 1 cache.

Increasing the amount of work executing on processors effectively dedicated to a single LPAR (“Vertical High CPs”) reduces the frequency of multiple LPARs with disparate workloads competing for the same processor cache, which is particularly detrimental to processor efficiency and throughput.

MLC Savings of Millions of Dollars

In my specific experience, operating at percent utilizations in the 30’s instead of the upper 80’s reduced MSU consumption by 30% (13,000 MIPS!), resulting in year-after-year Monthly License Charge (MLC) software savings of millions of dollars annually.

[You can download the presentation notes with more details on how this was accomplished here]. The economics of one-time hardware acquisitions creating “forevermore” annual software savings of this magnitude are readily apparent.

This experience ultimately turned all my concepts of mainframe capacity planning upside down, because processor cache operates far more effectively at lower utilization levels. Like Alice Through the Looking Glass, I’m now walking upside down with new insights!

 

MIPS vs. Transactions report from the presentation

Figure 1: MIPS vs. Transactions report from the presentation

 

Read my follow-up to this blog to learn how other mainframe sites have identified 7-figure annual MLC reduction savings.

Related

Blog

zIIPing Along

Despite the benefits - zIIP processors are typically less expensive to purchase and also run at full speed on sub-capacity CPU models - zIIP processor usage may not always be what one hopes for.

Read more
Blog

Managing the Gap in IT Spending and Revenue Growth in your Capacity Planning Efforts

Capacity planning is important, but don’t let the importance of future capacity needs for the budget drive you to overlook opportunities to building a bridge toward better performance and longer term efficiencies.

Read more
Blog

Throwing out the Rolling Four-Hour Average with Tailored Fit Pricing, Enterprise Consumption

The Rolling 4-Hour Average (R4HA) is a measurement of your average speed, over four hours; Tailored Fit Pricing measures precisely how far you drove.

Read more

Go to Resources

How to use Processor Cache Optimization to Reduce z Systems Costs

Optimizing processor cache can significantly reduce CPU consumption, and thus z Systems software costs, for your workload on modern z Systems processors. This paper shows how you can identify areas for improvement and measure the results, using data from SMF 113 records.

This article's author

Todd Havekost
Senior z/OS Performance Consultant
Read Todd's bio

Share this blog

Subscribe to our Newsletter

Subscribe to our newsletter and receive monthly updates about the latest industry news and high quality content, like webinars, blogs, white papers, and more.