Now that significant cycle speed improvements are a thing of the past, delivered capacity on processors beginning with the z13 is more dependent than ever before on effective utilization of processor cache.
Since it is likely that one-third to more than half of your total CPU cycles are spent waiting for data and instructions to be staged into level 1 processor cache, it is critical to understand and have visibility into this significant component of your CPU consumption.
Multiple case studies using processor cache metrics to identify the impact of z15 upgrades on delivered capacity will be the primary focus of this session.
z14 and z15 processor cache design changes will also be covered in detail.
And many specific actions that may help you optimize processor cache in your current environment will be presented, accompanied by before-and-after data quantifying the CPU reductions others have achieved by implementing these actions.
More IntelliMagic zAcademy Sessions
Metro Global Mirror (MGM) Monitoring in GDPS Sites | IntelliMagic zAcademy
This webinar will will provide practical advice about monitoring the recovery point objective (RPO) and factors affecting RPO.
MQ: How to Extract Insights and Optimize Performance Using SMF Data | IntelliMagic zAcademy
This webinar will introduce you to best practices for enhancing your analysis of MQ Statistics (SMF 115) and Accounting (116) data.
Where Are All The Performance Analysts? - A Mainframe Roundtable | IntelliMagic zAcademy
We have brought together industry experts from across the board to discuss the importance of having an efficient team managing the performance of their business applications.