How Moving zEDC to NXU Enhanced Compression Throughput and Elapsed Time

Facing well-known limitations on potential improvements to cycle speed, IBM has been actively pursuing other approaches to achieve throughput and performance improvements in new generations of Z processors.

The focus of this Cheryl Watson’s Tuning Letter article is on one of the improvements related to the Integrated Accelerator for zEnterprise Data Compression (zEDC). It is implemented in the Nest Accelerator Unit (NXU) on each z15/z16 processor chip. Moving this hardware compression functionality from PCIe Express cards in I/O drawers (originally introduced with zEC12 processors) to the on-chip NXU provides significant improvements in compression throughput and elapsed time. This zEDC functionality is delivered with every z15/z16 T01 and T02 at no additional charge.

Moving the compression function from PCIE-attached zEDC cards to the zEDC Accelerator has resulted in changes (reductions) in the metrics that are available. One of the objectives of this short article is to help you understand what has changed, what information is still available, and where that information is obtained from.


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This document is reprinted with permission from Watson and Walker. It originally appeared in Cheryl Watson’s Tuning Letter 2021 No. 3. The functionality changes and optimization opportunities cited for the z15 in this article are also fully applicable to the z16.

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