Achieving CPU (& MLC) Savings on z13 and z14 Processors

 

email iconGet Notified of Webinars

Beginning with z13 processors and continuing with z14s, customer experiences have confirmed that delivered capacity is more dependent than ever before on effective utilization of processor cache. This session covers how to interpret the SMF 113 metrics to optimize your environment and reduce CPU consumption and MLC software expense, and reflects findings from analyzing detailed processor cache data from 50 sites.

Details on z14 cache design changes will be presented and assessed using metrics from a z14 migration case study.

Insights into the potential impact of various tuning actions will be brought to life with data from numerous real-life case studies. This session builds upon a related user experience presentation that was selected for the 2016 “SHARE Best Session” award and 2017 “CMG Best Paper Award,” but has been significantly expanded with knowledge and experiences gained from reviewing data from dozens of sites.

Related Resources

Blog

Why Am I Still Seeing zIIP Eligible Work?

zIIP-eligible CPU consumption that overflows onto general purpose CPs (GCPs) – known as “zIIP crossover” - is a key focal point for software cost savings. However, despite your meticulous efforts, it is possible that zIIP crossover work is still consuming GCP cycles unnecessarily.

Read more
Blog

Top ‘IntelliMagic zAcademy’ Webinars of 2023

View the top rated mainframe performance webinars of 2023 covering insights on the z16, overcoming skills gap challenges, understanding z/OS configuration, and more!

Read more
Cheryl Watson's Tuning Letter

Making Sense of the Many I/O Count Fields in SMF | Cheryl Watson's Tuning Letter

In this reprint from Cheryl Watson’s Tuning Letter, Todd Havekost addresses a question about the different fields in SMF records having different values.

Read more

Go to Resources