How are the newest mainframe processor architectures affecting your z/OS mainframe software costs? How can you execute all your transactions and jobs with fewer MSU’s and no performance hit? Join one of the leading MLC reduction experts in the country for a focus on processor cache optimization, also touching on some additional MLC reduction methods.
This session will:
- Challenge some long held assumptions about CPU utilization and processor cache optimization
- Cover metrics (such as RNI) and a real world case study that reduced peak MSU’s by more than 20%
- Demonstrate how a modernization of your SMF/RMF interpretation helps achieve efficiency and performance objectives
Mainframe Cost Savings Part 2: 4HRA, zIIP Overflow, XCF, and Db2 Memory
This blog covers several CPU reduction areas, including, moving work outside the monthly peak R4HA interval, reducing zIIP overflow, reducing XCF volumes, and leveraging Db2 memory to reduce I/Os.
Mainframe Cost Savings: Infrastructure Opportunities Part 1: Processor Cache
CPU optimization opportunities applicable across the infrastructure can often by implemented without the involvement of application teams and can benefit a significant portion (or all) of the work across the system.
Don’t Keep Your CPU Waiting: Speed Reading for Machines | IntelliMagic zAcademy
This webinar discusses the many tiers of storage in IT systems and offers ideas about how to optimize access to those areas.