How are the newest mainframe processor architectures affecting your z/OS mainframe software costs? How can you execute all your transactions and jobs with fewer MSU’s and no performance hit? Join one of the leading MLC reduction experts in the country for a focus on processor cache optimization, also touching on some additional MLC reduction methods.
This session will:
- Challenge some long held assumptions about CPU utilization and processor cache optimization
- Cover metrics (such as RNI) and a real world case study that reduced peak MSU’s by more than 20%
- Demonstrate how a modernization of your SMF/RMF interpretation helps achieve efficiency and performance objectives
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Why Am I Still Seeing zIIP Eligible Work?
zIIP-eligible CPU consumption that overflows onto general purpose CPs (GCPs) – known as “zIIP crossover” - is a key focal point for software cost savings. However, despite your meticulous efforts, it is possible that zIIP crossover work is still consuming GCP cycles unnecessarily.
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