Todd is a Senior z/OS Performance Consultant for IntelliMagic. His primary area of interest over the course of his 40 year IT career has been z/OS systems performance. Before joining IntelliMagic, Todd spent 26 years at USAA in a variety of roles including mainframe architect and leading their highly successful mainframe software expense reduction initiative.
Having been thoroughly impressed as a customer with the visibility IntelliMagic Vision provides into z/OS systems infrastructure, Todd joined IntelliMagic in 2016 and now helps customers leverage the product to maximize the value obtained from RMF/SMF metrics to automatically identify potential risks to availability and performance. He also leads IntelliMagic’s efforts to accelerate the reduction of Monthly License Charges for customers of IntelliMagic Vision.
Todd is a highly-regarded industry speaker and has given award winning presentations at events such as SHARE and CMG.
Resources created by Todd Havekost
Mainframe Cost Savings Part 2: 4HRA, zIIP Overflow, XCF, and Db2 Memory
This blog covers several CPU reduction areas, including, moving work outside the monthly peak R4HA interval, reducing zIIP overflow, reducing XCF volumes, and leveraging Db2 memory to reduce I/Os.
Mainframe Cost Savings: Infrastructure Opportunities Part 1: Processor Cache
CPU optimization opportunities applicable across the infrastructure can often by implemented without the involvement of application teams and can benefit a significant portion (or all) of the work across the system.
Integrating Dataset Performance (SMF 42.6) and Db2 Buffer Pools & Databases (SMF 102/IFCID 199) Data
Dataset performance data from SMF 42.6 records provides disk cache and response time data at the Db2 buffer pool and Db2 database levels when integrated with Db2 Statistics IFCID 199 data.
Leveraging XCF Message Activity for CPU Efficiency
The examples in this blog demonstrate how intuitive visibility into XCF message volumes combined with metrics from various XCF callers help provide a complete picture of the services XCF is performing.
Address Space and Db2 Accounting Data
Learn how address space (SMF 30) and Db2 Accounting (SMF 101) data provide a more complete “big picture” view when integrated than is available from either data source on its own.
Troubleshooting WLM Missed Goals with CICS Transaction Data
Combined CICS and z/OS Systems visibility enables easy troubleshooting and root cause analysis of missed WLM goals resulting from CICS transaction data.
Db2 Buffer Pool Tuning: Exploring Key Metrics (Part 2)
Easy accessibility to key Db2 buffer metrics simplifies buffer pool tuning analyses, increasing the likelihood they will be periodically revisited using data from new time intervals.
Db2 Buffer Pool Tuning: Exploring Key Metrics (Part 1)
Easy accessibility to key Db2 buffer metrics enhances buffer pool tuning analyses so that they can be quickly completed. This video explores key metrics for one buffer pool tuning methodology.
Deriving Insights from SMF 115 MQ Statistics Data
SMF 115 MQ Statistics records report metrics at the MQ queue manager level. These records are lightweight and have negligible CPU cost, so sites typically generate MQ Statistics records on an ongoing basis.
MQ Statistics - Learning From SMF
This article is designed to introduce you to the types of insights that are available through SMF data with a focus on the SMF 115 MQ Statistics data.
Sub-Capacity Reporting Tool (SCRT) Filtering Capabilities & Benefits
The goal of analyzing Sub-Capacity Reporting Tool (SCRT) usage is to ultimately manage and reduce your MSU usage, and thus MLC costs.
Avoid MLC Charges on Unintended Usage Data Using SMF 89 Records
The SMF 89 record type stores the CPU of each registered Sub-Capacity product over time. This is useful for avoiding MLC charges on unintended usage and much more.
Avoid Inefficiencies with Store Into Instruction Stream (SIIS) Assessments
Programs that store data into the instruction stream introduce major inefficiencies into CPU performance. Updating SIIS programs can result in significant reduction of CPU utilization.
Mainframe Security’s Latest Tool for Ensuring Encryption Standards are Met
zERT data can enable the mainframe security team to both evaluate ongoing adherence to security policies and programmatically provide data for required reporting to auditors and compliance officers.
Imagine How Much You Can Learn from SMF Data – Part 1
For both novices and experts, learning is greatly expedited by having easy visibility into SMF data so that all the time can be spent exploring, analyzing, and learning.
Deriving Value when Deluged with Data (aka CICS Transaction Reporting)
When searching for the response time of certain CICS transactions, you need an easy and effective way to filter out the noise and rapidly find what you’re looking for.
Impact of z14 on Processor Cache and MLC Expenses
This article examines the changes in processor cache design for the z14 processor model.
Lower MLC Software Costs with Processor Cache Optimization
Processor cache utilization plays a significant role in CPU consumption for all Z processors, but that role is more prominent than ever on z13 models.
How to use Processor Cache Optimization to Reduce z Systems Costs
Optimizing processor cache can significantly reduce CPU consumption, and thus z Systems software costs, for your workload on modern z Systems processors.
Reduce MLC Software Costs by Optimizing LPAR Configurations
This article focuses on changes to LPAR configurations that can improve cache efficiency, as reflected in lower Relative Nest Intensity (RNI) values.
zHyperLink - Coming to a Data Center Near You (Sooner Than You Think)
Customer responses in a recent zHyperLink webinar indicate their need for I/O latency improvements will drive near-term efforts to overcome potential obstacles for data center configurations and replication solutions
5 Key Attributes of an Effective Solution to the z/OS Performance Skills Gap
The skills shortage for z/OS performance analysts and capacity planners has left many organizations struggling to ensure availability.
Beat the Annual MLC Software Price Increase
MLC costs already consume the largest chunk of many sites mainframe budgets. Here's how you can beat the MLC price increase.
Achieving CPU (& MLC) Savings on z13 and z14 Processors by Optimizing Processor Cache
Beginning with z13 processors and continuing with z14s, customer experiences have confirmed that delivered capacity is more dependent than ever before on effective utilization of processor cache.
Identify z/OS Performance Relationships & Trends
Performance analysts are greatly aided by the capability to easily view the relationships between various metrics by combining any metrics from the same data category
Optimizing MLC Software Costs with Processor Configurations
Significant opportunities to reduce CPU consumption and MLC expense may not be realized without understanding the vital role processor cache plays in CPU consumption.
Learn New z/OS Performance Skills Quickly - Cryptographic Data
Having a tool at your disposal that doesn’t require years to learn how to use overcomes one of the steepest initial barriers to effective analysis and greatly expedites learning.
Mainframe Capacity “Through the Looking Glass”
When processor cache is optimized, mainframe processors remain productive by actively executing instructions rather than unproductively burning cycles.
Todd Havekost Joins IntelliMagic to Help IBM Mainframe Customers Reduce MLC
May 6, 2016 | IntelliMagic is pleased to announce the hire of Todd Havekost from USAA, where he served as Mainframe Architect and also led their Mainframe Software
Expense Reduction initiative.
Reporting on Group Capping and Usage
This video demonstrates reporting that provides visibility into the interrelationships between several key metrics when group or LPAR-based (“soft”) capping is in effect.
Todd Havekost of IntelliMagic awarded “Best Paper” at the CMG National Conference
Nov 01, 2017 | Todd Havekost has been awarded for his paper "Achieving CPU (& MLC) Savings through Optimizing Processor Cache". The paper focuses on how effective utilization of processor cache is critical to achieve rated CPU capacity for z13 and z14 processors.