Todd Havekost

This blog covers several CPU reduction areas, including, moving work outside the monthly peak R4HA interval, reducing zIIP overflow, reducing XCF volumes, and leveraging Db2 memory to reduce I/Os.

CPU optimization opportunities applicable across the infrastructure can often by implemented without the involvement of application teams and can benefit a significant portion (or all) of the work across the system.

Dataset performance data from SMF 42.6 records provides disk cache and response time data at the Db2 buffer pool and Db2 database levels when integrated with Db2 Statistics IFCID 199 data.

The examples in this blog demonstrate how intuitive visibility into XCF message volumes combined with metrics from various XCF callers help provide a complete picture of the services XCF is performing.

Learn how address space (SMF 30) and Db2 Accounting (SMF 101) data provide a more complete “big picture” view when integrated than is available from either data source on its own.

Combined CICS and z/OS Systems visibility enables easy troubleshooting and root cause analysis of missed WLM goals resulting from CICS transaction data.

Easy accessibility to key Db2 buffer metrics simplifies buffer pool tuning analyses, increasing the likelihood they will be periodically revisited using data from new time intervals.

Easy accessibility to key Db2 buffer metrics enhances buffer pool tuning analyses so that they can be quickly completed. This video explores key metrics for one buffer pool tuning methodology.

SMF 115 MQ Statistics records report metrics at the MQ queue manager level. These records are lightweight and have negligible CPU cost, so sites typically generate MQ Statistics records on an ongoing basis.

This article is designed to introduce you to the types of insights that are available through SMF data with a focus on the SMF 115 MQ Statistics data.

The goal of analyzing Sub-Capacity Reporting Tool (SCRT) usage is to ultimately manage and reduce your MSU usage, and thus MLC costs.

The SMF 89 record type stores the CPU of each registered Sub-Capacity product over time. This is useful for avoiding MLC charges on unintended usage and much more.

Programs that store data into the instruction stream introduce major inefficiencies into CPU performance. Updating SIIS programs can result in significant reduction of CPU utilization.

zERT data can enable the mainframe security team to both evaluate ongoing adherence to security policies and programmatically provide data for required reporting to auditors and compliance officers.

For both novices and experts, learning is greatly expedited by having easy visibility into SMF data so that all the time can be spent exploring, analyzing, and learning.

When searching for the response time of certain CICS transactions, you need an easy and effective way to filter out the noise and rapidly find what you’re looking for.

This article examines the changes in processor cache design for the z14 processor model.

Processor cache utilization plays a significant role in CPU consumption for all Z processors, but that role is more prominent than ever on z13 models.

Optimizing processor cache can significantly reduce CPU consumption, and thus z Systems software costs, for your workload on modern z Systems processors.

This article focuses on changes to LPAR configurations that can improve cache efficiency, as reflected in lower Relative Nest Intensity (RNI) values.

Customer responses in a recent zHyperLink webinar indicate their need for I/O latency improvements will drive near-term efforts to overcome potential obstacles for data center configurations and replication solutions

The skills shortage for z/OS performance analysts and capacity planners has left many organizations struggling to ensure availability.

MLC costs already consume the largest chunk of many sites mainframe budgets. Here's how you can beat the MLC price increase.

Beginning with z13 processors and continuing with z14s, customer experiences have confirmed that delivered capacity is more dependent than ever before on effective utilization of processor cache.

Performance analysts are greatly aided by the capability to easily view the relationships between various metrics by combining any metrics from the same data category

Significant opportunities to reduce CPU consumption and MLC expense may not be realized without understanding the vital role processor cache plays in CPU consumption.

Having a tool at your disposal that doesn’t require years to learn how to use overcomes one of the steepest initial barriers to effective analysis and greatly expedites learning.

When processor cache is optimized, mainframe processors remain productive by actively executing instructions rather than unproductively burning cycles.

May 6, 2016 | IntelliMagic is pleased to announce the hire of Todd Havekost from USAA, where he served as Mainframe Architect and also led their Mainframe Software
Expense Reduction initiative.

This video demonstrates reporting that provides visibility into the interrelationships between several key metrics when group or LPAR-based (“soft”) capping is in effect.